Crystalline OS/Si Hybrid OSLSI®Structure
Infinite Potential of CAAC-OS®


Application of OSLSI® to memory, CPU, and FPGA


The hybrid structure where a crystalline oxide semiconductor, CAAC-OS, is stacked on a silicon CMOS circuit realizes signal processing LSI devices with unprecedentedly low power consumption. The extremely low off-state current of a crystalline oxide semiconductor FET (hereinafter OSFET®) can realize super low power of electronic devices such as a memory, a CPU, an FPGA, and an image sensor.



▲ Crystalline OS/Si hybrid LSI structure and its physical properties and characteristics


High performance devices using crystalline oxide semiconductors





DOSRAM®

（Dynamic Oxide Semiconductor Random Access Memory）

Super-low-power device enabled by significantly reducing refresh operations
Presented at VLSI 2019 and awarded Highlighted paper


DOSRAM is based on DRAM and has a memory cell that consists of one transistor and one capacitor like DRAM.
With the use of OSFETs, DOSRAM can realize high speed operation and reduce the refresh rate to several times per hour to several times per year, whereas conventional DRAM needs refresh operations with the interval of milliseconds or less.
Moreover, the OS/Si hybrid structure enables stacking of a sense amplifier array and a DOSRAM cell array, thereby reducing energy for data writing/reading[1].

[1] T. Onuki et al., “Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated with 65-nm Si CMOS”, IEEE Symp. VLSI Circuits Dig. Tech. Pap., 125 (2016).



NOSRAM®

（Non-volatile Oxide Semiconductor Random Access Memory）

Memory with potentially limitless writing cycles

This is a new voltage-controlled nonvolatile memory that utilizes the extremely low off-state current of OSFET®. This memory achieves unlimited writing cycles and high-speed writing of multi-level data at low power.

In a NOSRAM cell, data is stored by holding a charge (see the lower right figure). For this structure, more information can be stored in a single cell by suppressing variations between elements and finely controlling the writing voltage. SEL developed a 4bit-per-cell NOSRAM in 2014[2][3], and now SEL has achieved 6 bits per cell (64 levels) with a voltage distribution width of 25 mV, demonstrating a possibility for a never-before-seen high-density memory device.

nosram

[2] Demonstrated at “Display Innovation 2014”, October 29 to 31, 2014, Pacifico Yokohama, Japan.
[3] T. Matsuzaki et al., “A 128kb 4b/cell Nonvolatile Memory with Crystalline In-Ga-Zn Oxide FET Using Vt Cancel Write Method”, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Pap., 125 (2015).



NoffMCU™

(Normally-off driving1) Microcontroller Unit (MCU) )

Microcontroller NoffMCU including NoffCPU
Realizing extremely low power consumption and quick startup by application of CAAC-OS
Presented at VLSI 2019 and awarded Highlighted paper

Microcontrollers are formed by application of CAAC-OS to a CPU (NoffCPU), a memory cell, and a regulator circuit. In particular, the use of CAAC-OS in a regulator circuit allows a CPU and a memory to retain data even in a sleep mode. Furthermore, the state of a power source circuit (an analog potential) can also be retained with zero-power consumption, thereby successfully minimizing power consumption (standby power) in a sleep mode without affecting the startup time to an active mode. The application of CAAC-OS enabled microcontrollers with extremely low power consumption and quick startup[4].



1) Normally-off driving: Normally-off driving is a technology to reduce the power consumption of a CPU by turning off the power while in standby. In a typical CPU, the data is lost when it is turned off. Therefore, data transfer is needed every time the power is turned off for normally-off driving, leading to hindrance of power reduction. However, a CPU using OSFET can hold the internal state even when the power is shut off, resulting in a low-power-consumption CPU that enables efficient on/off operation and requires no power while being in standby.


Data retention in a sleep mode reduced standby power to 1/300.

NoffMCU with CAAC-OS can retain data even in a sleep mode
While maintaining the startup time from a sleep mode to an active mode, the power consumption (standby power) in the sleep mode has been successfully reduced to 1/300 compared to the case where data is not retained during the sleep mode.



[Conventional technology] If data is not retained in a sleep mode..
Large power consumption (standby power) in a sleep mode increases the overall power consumption. Conventional technologies have a trade-off between sleep mode power and startup time; lower sleep mode power results in longer time to start up.


[4] © 2019 IEEE. Reprinted, with permission, from T. Ishizu, et al., Symp. VLSI Tech. Dig., 2019, C48-C49




NoffCPU®

（Normally-Off Central Processing Unit）

Retention of internal data in the power-off
SEL succeeded in lowering the power consumption

NoffCPU can be efficiently driven in a normally-off manner utilizing the extremely low off-state current of the OSFET. For our report of the 8-bit CPU[5] in 2012, we have won an SSDM Best Paper Award. In 2013, we prototyped a 32-bit CPU[6]. The NoffCPU uses a nonvolatile flip-flop (FF) for the register in the CPU and a non-volatile memory for a memory. It has features of instant on/off operation and no power consumption in standby.

[5] T. Ohmaru et al., “Eight-bit CPU with Nonvolatile Registers Capable of Holding Data for 40 Days at 85℃ Using Crystalline In-Ga-Zn Oxide Thin Film Transistors”, Ext. Abstr. Solid State Dev. Mater., 1144 (2012).
[6] Reported with ARM and NOKIA. H. Tamura et al., “Embedded SRAM and Cortex-M0 core using a 60-nm crystalline oxide semiconductor”, IEEE Micro, 34, 42 (2014).



FPGA

（Field Programmable Gate Array）

Reconfigurable logic circuit with no need for wire reconnection at each time of power-on
Presented at ISSCC 2014

FPGA is an integrated circuit where the user can change the connection of internal wiring. Since NOSRAM is used to store the connection configurations of the wires, there is no need to reconnect the wires when the power is turned on, unlike typical FPGA[7].

[7] c2014 IEEE. Reprinted, with permission, from T. Aoki, et al., Int. Solid-State Circuit Conf. Dig. Tech. Pap., 2014, pp.502-503



Image Sensor

Presented at ISSCC 2015.
Three modes realizing a reduction in power consumption.

There are three modes: an imaging mode, which outputs captured data in pixel units; a motion capture mode, which uses an analog processor to process differential data; and a standby mode, which reduces power consumption after motion capture in each frame. Power consumption can be reduced by operation of only a circuit block required for each mode[8].

[8] T. Aoki et al., “Electronic Global Shutter CMOS Image Sensor using oxide semiconductor FET with Extremely Low Off-state Current”, IEEE Symp. VLSI Circuits Dig. Tech. Pap., 174 (2011).


* OSLSI, CAAC-OS, OSFET, NoffCPU, NOSRAM, DOSRAM, BTOS, NoffMCU are registered trademarks or trademarks of Semiconductor Energy Laboratory Co., Ltd. (Japanese trademark registration No. 5698906, No. 5473535, No. 5519759, No. 6544563, No. 6544564, and No. 6146374). Cortex is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.